1. Field of the Invention
This invention relates to processors, and more particularly, to prefetchers.
2. Description of the Related Art
Cache memories figure prominently in the performance of computer system processors. As processor technology has advanced and the demand for performance has increased, the number and capacity of cache memories has followed. Some processors may have a single cache or single level of cache memory, while others may have multiple levels of caches. Cache memories may be defined by levels, based on their proximity to execution units of a processor core. For example, a level one (L1) cache may be the closest cache to the execution unit(s), a level two (L2) cache may be the second closest to the execution unit(s), and an level three (L3) cache may be the third closest to the execution unit(s).
Data may be typically loaded into a cache memory responsive to a cache miss. A cache miss occurs when requested data is not found in the cache. Cache misses are undesirable, as the performance penalty associated with a cache miss can be significant. Accordingly, some processors employ one or more prefetchers. A prefetcher may analyze data access patterns in order to predict from where in memory future accesses will be performed. Based on these predictions, the prefetcher may then obtain data from the memory and store it into the cache. In processors having multiple prefetchers, the different prefetchers may utilize different algorithms to independently and concurrently prefetch data into a cache. Accordingly, one prefetcher may store information into a cache using stride prefetching (loading data located at fixed address intervals from one another), while another prefetcher may store information into the cache based on instruction pointer (IP) data.